document number: 91257 www.vishay.com s-81368-rev. a, 21-jul-08 1 power mosfet irfps35n50l, sihfps35n50l vishay siliconix features ? super fast body diode eliminates the need for external diodes in zvs applications ? lower gate charge results in simpler drive requirements ? enhanced dv/dt capabilities offer improved ruggedness ? higher gate voltage threshold offers improved noise immunity ? lead (pb)-free available applications ? zero voltage switching smps ? telecom and server power supplies ? uninterruptible power supplies ? motor control applications notes a. repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. starting t j = 25 c, l = 0.97 mh, r g = 25 , i as = 34 a (see fig. 12). c. i sd 34 a, di/dt 765 a/s, v dd v ds , t j 150 c. d. 1.6 mm from case. product summary v ds (v) 500 r ds(on) ( )v gs = 10 v 0.125 q g (max.) (nc) 230 q gs (nc) 65 q gd (nc) 110 configuration single g d s super-247 tm n - c hannel m os fet g d s a v aila b le rohs* compliant ordering information package super-247 tm lead (pb)-free IRFPS35N50LPBF sihfps35n50l-e3 snpb irfps35n50l sihfps35n50l absolute maximum ratings t c = 25 c, unless otherwise noted parameter symbol limit unit drain-source voltage v ds 500 v gate-source voltage v gs 30 continuous drain current v gs at 10 v t c = 25 c i d 34 a t c = 100 c 22 pulsed drain current a i dm 140 linear derating factor 3.6 w/c single pulse avalanche energy b e as 560 mj repetitive avalanche current a i ar 34 a repetitive avalanche energy a e ar 45 mj maximum power dissipation t c = 25 c p d 450 w peak diode recovery dv/dt c dv/dt 15 v/ns operating junction and storage temperature range t j , t stg - 55 to + 150 c soldering recommendations (p eak temperature) for 10 s 300 d mounting torque 6-32 or m3 screw 10 lbf in 1.1 n m * pb containing terminations are not rohs compliant, exemptions may apply
www.vishay.com document number: 91257 2 s-81368-rev. a, 21-jul-08 irfps35n50l, sihfps35n50l vishay siliconix note a. r th is measured at t j approximately 90 c. notes a. repetitive rating; pulse width limited by maximum junction temper ature (see fig. 11). b. pulse width 400 s; duty cycle 2 %. c. c oss eff. is a fixed capacitance that gi ves the same charging time as c oss while v ds is rising from 0 to 80 % v ds . c oss eff. (er) is a fixed capacitance that stores the same energy as c oss while v ds is rising from 0 to 80 % v ds . thermal resistance ratings parameter symbol typ. max. unit maximum junction-to-ambient r thja -40 c/w case-to-sink, flat, greased surface r thcs 0.24 - maximum junction-to-case (drain) r thjc -0.28 specifications t j = 25 c, unless otherwise noted parameter symbol test conditions min. typ. max. unit static drain-source breakdown voltage v ds v gs = 0 v, i d = 250 a 500 - - v v ds temperature coefficient v ds /t j reference to 25 c, i d = 1 ma -0.12- v/c gate-source threshold voltage v gs(th) v ds = v gs , i d = 250 a 3.0 - 5.0 v gate-source leakage i gss v gs = 30 v -- 100 na zero gate voltage drain current i dss v ds = 500 v, v gs = 0 v -- 50 a v ds = 400 v, v gs = 0 v, t j = 125 c -- 2.0 ma drain-source on-state resistance r ds(on) v gs = 10 v i d = 20 a b - 0.125 0.145 forward transconductance g fs v ds = 50 v, i d = 20 a b 18 - - s dynamic input capacitance c iss v gs = 0 v, v ds = 25 v, f = 1.0 mhz, see fig. 5 - 5580 - pf output capacitance c oss - 590 - reverse transfer capacitance c rss -58- output capacitance c oss v gs = 0 v v ds = 1.0 v , f = 1.0 mhz - 7290 - v ds = 400 v , f = 1.0 mhz - 160 - effective output capacitance c oss eff. v ds = 0 v to 400 v c - 320 - effective output capacitance (energy related) c oss eff. (er) - 220 - total gate charge q g v gs = 10 v i d = 34 a, v ds = 400 v, see fig. 7 and 13 b -- 230 nc gate-source charge q gs -- 65 gate-drain charge q gd -- 110 internal gate resistance r g f = 1 mhz, open drain - 1.1 - turn-on delay time t d(on) v dd = 250 v, i d = 34 a, r g = 1.2 , see fig. 10 b -24- ns rise time t r - 100 - turn-off delay time t d(off) -42- fall time t f -42- drain-source body diode characteristics continuous source-drain diode current i s mosfet symbol showing the integral reverse p - n junction diode --34 a pulsed diode forward current a i sm - - 140 body diode voltage v sd t j = 25 c, i s = 34 a, v gs = 0 v b --1.5v body diode reverse recovery time t rr t j = 25 c, i f = 34 a - 170 250 ns t j = 125 c, di/dt = 100 a/s b - 220 330 body diode reverse recovery charge q rr t j = 25 c, i s = 34 a, v gs = 0 v b - 670 1010 c t j = 125 c, di/dt = 100 a/s b - 1500 2200 reverse recovery current i rrm t j = 25 c - 8.5 - a forward turn-on time t on intrinsic turn-on time is neglig ible (turn-on is dominated by l s and l d ) s d g
document number: 91257 www.vishay.com s-81368-rev. a, 21-jul-08 3 irfps35n50l, sihfps35n50l vishay siliconix typical characteristics 25 c, unless otherwise noted fig. 1 - typical output characteristics fig. 2 - typical output characteristics fig. 3 - typical transfer characteristics fig. 4 - normalized on-resistance vs. temperature 0.1 1 10 100 v ds , drain-to-so u rce v oltage ( v ) 0.001 0.01 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 4.5 v 20 s pulse w idth tj = 25c v gs top 15 v 10 v 8 .0 v 7.0 v 6.0 v 5.5 v 5.0 v bottom 4.5 v 0.1 1 10 100 1000 0.1 1 10 100 20 s pulse w idth t = 150 c j top bottom v gs 15 v 10 v 8 .0 v 7.0 v 6.0 v 5.5 v 5.0 v 4.5 v v , drain-to-so u rce v oltage ( v ) i , drain-to-so u rce c u rrent (a) ds d 4.5 v 0.01 0.1 1 10 100 1000 4.0 5.0 6.0 7.0 8 .0 9.0 10.0 v = 50 v 20 s pulse w idth ds v , gate-to-so u rce v oltage ( v ) i , drain-to-so u rce c u rrent (a) gs d t = 25 c j t = 150 c j -60 -40 -20 0 20 40 60 8 0 100 120 140 160 0.0 0.5 1.0 1.5 2.0 2.5 3.0 t , j u nction temperat u re ( c) r , drain-to-so u rce on resistance ( n ormalized) j ds(on) v = i = gs d 10 v 34a
www.vishay.com document number: 91257 4 s-81368-rev. a, 21-jul-08 irfps35n50l, sihfps35n50l vishay siliconix fig. 5 - typical capacitance vs. drain-to-source voltage fig. 6 - typical output capacitance stored energy vs. v ds fig. 7 - typical gate charge vs. gate-to-source voltage fig. 8 - typical source drain diode forward voltage 1 10 100 1000 v ds , drain-to-so u rce v oltage ( v ) 10 100 1000 10000 100000 c , c a p a c i t a n c e ( p f ) coss crss ciss v gs = 0 v , f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd 0 100 200 300 400 500 600 v ds, drain-to-so u rce v oltage ( v ) 0 5 10 15 20 25 30 e n e r g y ( j ) 0 40 8 0 120 160 200 240 0 4 8 12 16 20 q , total gate charge (nc) v , gate-to-so u rce v oltage ( v ) g gs for test circuit see figure i = d 13 34a v = 100 v ds v = 250 v ds v = 400 v ds 0.1 1 10 100 1000 0.2 0.4 0.6 0. 8 1.0 1.2 1.4 1.6 v ,so u rce-to-drain v oltage ( v ) i , re v erse drain c u rrent (a) sd sd v = 0 v gs t = 25 c j t = 150 c j
document number: 91257 www.vishay.com s-81368-rev. a, 21-jul-08 5 irfps35n50l, sihfps35n50l vishay siliconix fig. 9 - maximum drain current vs. case temperature fig. 10a - switching time test circuit fig. 10b - switching time waveforms fig. 11 - maximum effective transient thermal impedance, junction-to-case fig. 12a - unclamped inductive test circui t fig. 12b - unclamped inductive waveforms 25 50 75 100 125 150 0 5 10 15 20 25 30 35 t , case temperat u re ( c) i , drain c u rrent (a) c d p u lse w idth 1 s d u ty factor 0.1 % r d v gs r g d.u.t. 10 v + - v ds v dd v ds 90 % 10 % v gs t d(on) t r t d(off) t f 0.001 0.01 0.1 1 0.00001 0.0001 0.001 0.01 0.1 n otes: 1. d u ty factor d = t / t 2. peak t = p x z + t 1 2 j dm thjc c p t t dm 1 2 t , rectang u lar p u lse d u ration (sec) thermal response (z ) 1 thjc 0.01 0.02 0.05 0.10 0.20 d = 0.50 si n gle pulse (thermal respo n se) a a r g i as 0.01 t p d.u.t l v ds + - v dd dri v er a 15 v 20 v i as v ds t p
www.vishay.com document number: 91257 6 s-81368-rev. a, 21-jul-08 irfps35n50l, sihfps35n50l vishay siliconix fig. 12c - maximum avalanche energy vs. drain current fig. 13a - gate charge test circuit fig. 12d - maximum safe operating area fig. 13b - basic gate charge waveform 25 50 75 100 125 150 0 200 400 600 8 00 1000 1200 starting t , j u nction temperat u re ( c) e , single p u lse a v alanche energy (mj) j as i d top bottom 15a 22a 34a d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v c u rrent reg u lator c u rrent sampling resistors same type as d.u.t. + - 1 10 100 1000 1 10 100 1000 10000 operatio n i n this area limited by r ds(on) single p u lse t t = 150 c = 25 c j c v , drain-to-so u rce v oltage ( v ) i , drain c u rrent (a) i , drain c u rrent (a) ds d 10 u s 100 u s 1ms 10ms d.u.t. 3 ma v gs v ds i g i d 0.3 f 0.2 f 50 k 12 v c u rrent reg u lator c u rrent sampling resistors same type as d.u.t. + -
document number: 91257 www.vishay.com s-81368-rev. a, 21-jul-08 7 irfps35n50l, sihfps35n50l vishay siliconix fig. 14 - for n-channel vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91257. p. w . period di/dt diode reco v ery d v /dt ripple 5 % body diode for w ard drop re-applied v oltage re v erse reco v ery c u rrent body diode for w ard c u rrent v gs = 10 v * v dd i sd dri v er gate dri v e d.u.t. i sd w a v eform d.u.t. v ds w a v eform ind u ctor c u rrent d = p. w . period + - + + + - - - * v gs = 5 v for logic le v el de v ices peak diode recovery dv/dt test circuit v dd ? d v /dt controlled b y r g ? dri v er same type as d.u.t. ? i sd controlled b y d u ty factor "d" ? d.u.t. - de v ice u nder test d.u.t circ u it layo u t considerations ? lo w stray ind u ctance ? gro u nd plane ? lo w leakage ind u ctance c u rrent transformer r g
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